SoC Builder RTL Dataset v1 (Experiment)

SoC Builder RTL Dataset — v1 (Experiment Release) A reproducible, machine-generated corpus of synthesizable System-on-Chip (SoC) RTL designs for machine learning on hardware: RTL representation learning today, and — as the corpus grows — netlist, timing, and placement prediction. Every design is a complete, hierarchical, lint-clean Verilog SoC assembled from real open-source IP — RISC-V CPU cores, network-on-chip (NoC) interconnects, accelerators, peripherals, memories and… See the full description on the dataset page:

Source: Hugging Face Hub (hasankursun/soc-builder-rtl-v1). Metadata imported from the dataset’s Hub tags.